The use of superjunction devices is becoming more and more widespread in the recent years. In a conventional n-channel superjunction device, p columns and n columns that are arranged alternately combine to form a compound buffer layer, which is used to replace the n-type epitaxial layer in an MOSFET device. A typical p column in the compound buffer layer is surrounded by adjacent n columns, and a typical n column is surrounded by adjacent p columns.
Taking superjunction transistors as an example, super-junction transistors can reach very high switching speed and very low switching losses due to the fast depletion of n and p columns at drain-source voltages VDS≦50V. This however can lead to increased ringing tendency which may result even in a destruction of the device. Therefore a very low gate drain capacitance CGD at high VDS should be avoided. Also an increase of gate source capacitance CGS may be desirable as this reduces the amplitude of the gate voltage VGS caused e.g. by feedback by inductive parasitic in the source connection or the raise of the drain voltage VDS. This can help for example to avoid dVDS/dt induced turn on under normal application conditions. On the other hand, under extreme dV/dt and dI/dt conditions like commutation, dVDS/dt induced turn on may be desirable.
To optimize a device for all this different needs, especially for trench cells which tend to have a higher transconductance, it is important to choose optimized CGD/CGS ratios as well as optimized absolute CGD and CDS values. Therefore, modification of the cell structure is required to tailor the device capacitances to the application requirements depending on VDS.
For power transistors, especially super-junction transistors, the gate pad is typically arranged on a thick oxide (field oxide) with a typical thickness ≧1 μm, or at least ≧500 nm. This has an advantage of higher bonding ruggedness for connecting the gate pad to a gate connection at the package with a wire bond. The capacitance depends on the size of the gate pad—and the area of additional metal lines distributing the gate potential on the chip like a gate runner or gate fingers—the oxide thickness as well as the doping under the gate pad. The capacitance of the gate pad can also help to optimize the device for the capacitance requirements optimizing the switching behavior.